7-6: Special Technologies 7-6-3: The Generic Technology

Special Arcs

The Universal arc in the Generic technology is able to make a connection between any two components, even if they are in different technologies. This is useful when mixing technologies while still maintaining proper connectivity, for example when simulating.

The Invisible arc attaches any two components, but makes no electrical connection. It is useful for constraining otherwise unrelated components.

The Unrouted arc makes arbitrary electrical connections, like the universal arc, but routers know to replace them with real geometry.

None of these arcs produce any actual geometry in IC descriptions, but they make important conceptual connections. Any existing arc in a normal technology can be converted to one of these three special arcs by using the Change... command (in menu Edit).

Special Nodes

There are also special nodes in the Generic technology. They are all available from the "Misc." entry of the component menu. A special primitive, called Cell Center, defines the origin of any cell. Once the node is placed, its location is at (0,0) for the cell. Since instances of the current cell use the origin as the anchor point for cursor-based references, the location of this node defines the anchor. For example, if you place this node in the upper-right corner of a cell, then creation commands place instances such that their upper-right corner is at the cursor. See Section 3-3 for more information on cell centers. A special primitive, called Essential Bounds, defines an alternate boundary of any cell. At least two of them must be placed in opposite corners, although 4 can be place to make it look better. Note that the Cell Center and Essential Bounds nodes are made "hard-to-select" by default, which means that they can be selected only by using "Special Select" mode (see Section 2-1-5 for more).

The Spice Code and Spice Declaration entries create text for Spice decks (see Section 9-4-3). The Verilog Code, Verilog Declaration, Verilog Parameter, and Verilog External Code entries create text for Verilog decks (see Section 9-4-2). These entries actually create Invisible Pin nodes with appropriate text on them.

A special primitive, called Simulation Probe is recognized by simulators and visually modified to reflect whatever it is connected to. The simulators that reflect the state of the circuit by drawing lines along arcs also fill-in these probe nodes. It provides a visual display of simulation activity, and works especially well with the VCR controls in the waveform window. See Section 4-11 for more.

The DRC Exclusion node is used by the design-rule checker (see Section 9-2-3). The Routing Exclusion node is used by routers to tell them to avoid certain layers under this node (see Section 9-6-1). Currently only the Sea-of-Gates router handles this. The AFG Exclusion node is used by the auto-fill generator (see Section 9-8-2).

The Invisible Pin is used for holding text, and it does not appear in hardcopy output (this is what is created when you use place Annotation Text). This pin can connect to any arc.

The Universal Pin is a node that can connect to any arc. This is useful as an intermediate component when replacing (first you replace the unwanted node with a Universal-Pin to allow it to fit with the existing arcs; then you replace the arcs; finally you put the desired new node in place).

The Unrouted Pin is used when joining unrouted arcs. It can also connect to anything.

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