The Electric VLSI Design System is a highly flexible and powerful system that can handle many different types of circuit design (MOS, Bipolar, schematics, printed circuitry, hardware description languages, etc.) It handles geometry at any angle (not just Manhattan) and can even handle curves.
Layout is done by placing and wiring electrical components. Although this is standard practice for schematics, it is unusual for chip layout. However, because of this style of design, Electric understands chip layout at a more sophisticated level, and can aid in design to an unprecedented degree.
The user interface is quite sophisticated and runs on all popular workstations (Windows, Macintosh, and UNIX). It also provides interpretive languages for advanced users.
The most interesting feature of the system is its global enforcement of connectivity which provides top-down design capability and ease of post-design modifications.
Electric has many analysis tools, including design-rule checking, simulation, and network comparison. Electric has many synthesis tools, including routing, compaction, silicon compilation, PLA generation, and compensation.
The incremental design-rule checker watches all changes made to the layout and displays error messages when violations are detected. It checks for spacing errors, notch errors, and minimum size violations.
A hierarchical design-rule checker does a thorough check of the circuit.
Electric can also read the output of Assura or Calibre and display the results.
The electrical-rule checker has two parts:
Electric comes with a built-in 12-state switch-level simulator, called ALS. An optional IRSIM simulation engine is available separately from Static Free Software. The simulator displays waveforms in a separate window and lets users cross-probe from either the waveform or the circuit window.
Electric is able to produce input decks for a number of popular simulators, including:
Users of Electric must obtain these simulators on their own.
The CMOS PLA generator works from a library of PLA elements, thus allowing customized arrays.
The Pad Frame generator places pad cells around a chip core and wires them together.
The ROM generator produces layout from a ROM personality file.
The compactor adjusts geometry to its minimal spacing in the X and Y axes.
Logical Effort is a system for marking digital schematic gates with fanout information that will produce optimally fast circuits.
Six experimental placement tools are available that use parallelism to speed the task.
The maze router runs single wires between points.
The cell stitching router make explicit connections where cells abut or overlap.
The mimic router watches user activity. When it sees a wire being created or deleted, it repeats the activity in similar situations throughout the circuit.
The river router runs multiple parallel wires in a channel between cells.
The sea-of-gates router makes arbitrary connections in the circuit.
Six experimental routers are available that use parallelism to speed the task.
The VHDL system can generate VHDL from a layout, and can compile VHDL to netlists of various format. These netlists can then be simulated with the built-in simulator, turned into layout with the silicon compiler, or saved to disk for use by external simulators.
The Silicon Compiler places and routes standard cells from a structural netlist (which can be obtained from VHDL which can be obtained from a schematic drawing).
The network consistency checker compares a layout with its equivalent schematic. It can also compare two different versions of a layout or two different versions of a schematic. An experimental version of NCC, called the Port Interchange Experiment, is also available.
This built-in system allows users to share a library of circuitry. Users can check out cells for editing and check them back in when done. Other users are prevented from changing checked-out cells, and can have their circuits updated when changes are checked in.
In addition, users are prevented from making changes to checked-out cells that would affect other cells that are not checked-out. Also, warnings are issued when multiple users check-out cells that are hierarchically related which may cause interference in their editing.
A second project management system, based on CVS, writes each cell to a separate disk file so CVS tools can manage the circuitry.
A Technology is an environment of design. Circuits can be built from any technology, and can even mix components from different technologies (to the extent that it is sensible).
Each technology is a collection of components and connecting wires. All relevant information is encapsulated in the technology, including design rules, simulation behavior, etc.
A build-in editor allows interactive creation of new technologies and modification of existing ones.
Electric has the following technologies:
nMOS | Generic N-channel MOS |
CMOS | Complementary MOS, many different versions: MOSIS Rules (6-metal, double-poly, scmos/submicron/deep) Generic Round (from Cal Tech) |
Bipolar | Generic Integrated Injector Logic |
BiCMOS | Hybrid of Bioplar and CMOS |
TFT | Thin-film |
Digital Filters | Generic arcitectural technology |
Printed Circuits | Handles up to 8-layer boards |
Schematics | Components for both analog and digital design |
FPGA | Custom FPGA design from architectural specification language |
Artwork | Elements for graphic design |
Electric reads and writes libraries of circuitry in its own binary format. For portability between computers, it is also able to read and write a textual format of its database. However, for maximum compatibility with other EDA systems, Electric supports a number of popular interchange and manufacturing formats:
Format | Direction | Description |
CIF | Input and Output | Caltech Intermediate Format |
GDS II | Input and Output | Calma GDS interchange format |
EDIF | Input and Output | Electronic Design Interchange Format |
SUE | Input | Schematic User Environment (a schematics editor) |
DXF | Input and Output | AutoCAD mechanical format |
VHDL | Input and Output | Hardware description language |
Verilog | Output | Hardware description language |
CDL | Output | Cadence's circuit description language |
EAGLE | Output | Schematic capture interface |
PADS | Output | Schematic capture interface |
ECAD | Output | Schematic capture interface |
Applicon | Input | Applicon/860 (an old CAD format) |
Bookshelf | Input | Bookshelf (placement interchange format) |
Gerber | Input and Output | Gerber Scientific plotter format |
HPGL | Output | Plotting language |
PostScript | Output | Plotting language |
SVG | Output | Scalable Vector Graphics (for browsers) |
The older, "C" version of Electric is fully internationalized, which means that it can be translated into other languages. The only translation that exists is French, and it is packaged with the source-code download.
The Electric User's Manual has been translated into Russian. This is an older version of the manual (6,06) and can be downloaded here.
To help spread the word about Electric, front-pages have been created in different languages. Each front page describes Electric briefly and then points the user to the main Static Free Software page, noting that the rest of the website is in English.
For those interested in doing a translation, please translate this page.
I already have translations in the following languages (thanks to all contributors):
After over 20 years as a C program, the Electric development team recoded the system in Java (this happened in 2003). Versions 8.00 and up are Java (the last C release was version 7.00).
Electric in Java is more stable in many ways, has a better user interface, and in many cases is faster than Electric in C. Some parts were just recoded, but other parts were completely rewritten. For example, the redisplay code was completely redone, and now runs nearly 10 times faster for whole-chip display. The NCC is entirely new also, and runs much faster. The Logical Effort code is also rewritten, and is much more powerful.
There are a few special cases of things that existed in "C" Electric and were not translated into Java. These items are either unimportant or obsolete: